The present invention generally relates to integrated circuits and more particularly to an improved integrated circuit design and method which utilizes voltage islands that operate at independent voltages and can be selectively gated to reduce power consumption.
As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.
The total power consumed by conventional CMOS circuitry is composed of two primary sources. The first is active power consumed by circuits as they switch states and either charge or discharge the capacitance associated with the switching nodes. Active power represents the power consumed by the intended work of the circuit to switch signal states and thus execute logic functions. This power is not present if the circuit in question is not actively switching. Active power is proportional to the capacitance that is switched, the frequency of operation, and to the square of the power supply voltage. Due to technology scaling, the capacitance per unit area increases with each process generation. The power increase represented by this capacitance increase is offset by the scaling of the power supply voltage, Vdd.
The frequency of operation, however, increases with each generation, leading to an overall increase in active power density from technology generation to technology generation. This increasing power density in turn drives the need for more expensive packaging, complex cooling solutions and decreased reliability due to increased temperatures. In addition to active power, there are components of leakage power, the most dominant of which is the sub-threshold current of the transistors in the circuit. As silicon technologies advance, smaller geometries become possible, enabling improvements of device structures including lower transistor oxide thickness (Tox), which in turn increases transistor performance. To maintain circuit reliability, Vdd must be lowered as Tox is reduced. As Vdd is reduced, the transistor threshold voltage (Vt) must be reduced in order to maintain or improve circuit performance, despite the drop in Vdd. This decrease in Vt and Tox then drives significant increases in leakage power, which has previously been negligible. As silicon technologies move forward, leakage currents become as important as active power in many applications. Therefore, there is a need for a method and structure that increases performance, while at the same time decreases power consumption. The invention described below satisfies these needs.
It is therefore an object of the present invention to provide a method of designing an integrated circuit chip that supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list that can include power, simulation, reliability, floorplanning, and/or timing information of each voltage island. The invention simulates the chip design using an unknown voltage state propagation on voltage island cell outputs identified by a power-on/off control signal within the voltage island specification list.
The invention also provides a method of designing an integrated circuit chip that supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list that has power and timing information of each voltage island and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
The invention performs physical placement of circuit elements on the integrated circuit chip according to a hierarchy established in the voltage island specification list. During the physical placement processing, limits are placed upon inserting logic elements within the voltage islands. The invention performs routing physical wiring within the integrated circuit chip according to a hierarchy established in the voltage island specification list. The invention constrains placement of physical pins to edges of the voltage islands adjacent power rings of a power supply within the integrated circuit chip. The specification list can include a power source name, a power source type, minimum voltage level, maximum voltage level, nominal voltage level, switching signal name, switching signal type, power on hours, and/or steady state on percentage.